1. Field of the Invention
The present invention relates to a phase blender and a multi-phase generator using the same, and more particularly to a phase blender for generating, by using input voltages having a phase difference, an output voltage corresponding to an intermediate phase, and a multi-phase generator for generating output voltages having an arbitrary phase difference by using the phase blender. The present application is based on Korean Patent Application No. 2001-8033, which is incorporated herein by reference.
2. Description of the Related Art
In order to realize the phase locked loop (PLL) or a delayed locked loop (DLL) as a clock generator using a phase blending mode, signals with diverse phases each delayed by a different amount are required to be inputted, or a phase blender which outputs various signals having a smaller phase difference than a phase difference of two inputted signals is required, as well as a multi-phase generator using such a phase blender.
It is referred to as xe2x80x9cdelay mixingxe2x80x9d or xe2x80x9cdelay interpolationxe2x80x9d to control a delay amount of an output signal with respect to two input signals having a delay difference, and an actual output signal is additionally delayed by a group delay of an entire system. In order to obtain such characteristics, an output signal may be generated by controlling a ratio of the current sources of two signals and adding the controlled ratio, and a fine-tap may be obtained by colliding two delayed signals using an inverter (related documents: B. W Garlepp et al., A portable digital DLL for high-speed CMOS interface circuit, IEEE J. Solid-state Circuits, vol. 34, pp.632-644, May 1999, and S. Sidiropoulos, High-performance interchip signaling, Ph.D. dissertation, Available as Tech. Rep. CLS-TR-98-760 from http://elib.stanford.edu Computer Systems Lab., Stanford University).
A phase blender inputs a selection code of N bits with respect to two inputs Vin1 and Vin2 having a delay time xcex94t and generates an output signal with the xcex94t divided by xc2xdN. Accordingly, a signal with a minimum delay time should be outputted in case that an N-bit code is xe2x80x980xe2x80x99, a signal with a maximum delay time should be outputted in case of 2Nxe2x88x921, and, in case that an arbitrary value between xe2x80x980xe2x80x99 and xe2x80x982Nxe2x88x921xe2x80x99, a signal with linear delay characteristics corresponding to the value should be outputted.
FIG. 1 shows a conventional phase blender. The phase blender shown in FIG. 1 takes a mode that generates an output signal having an intermediate delay amount by using an output of a CMOS inverter. A detailed description will be as follows (that two signals contrasted have a phase difference means that the two have a time difference as large as and corresponding to the phase difference in a time domain, so the same meaning applies to the phase difference and the time difference).
To a phase blender 20 are inputted two input voltages Vin1 and Vin2 having a phase difference, and the phase blender 20 outputs three output voltages Vout1, Vout2, and Vout3 having different phases from each other. The phase blender 20 has first and second phase delay units 21 and 22 to which the first and second input voltages Vin1 and Vin2 are respectively inputted, and an intermediate phase output unit 30 to which the first and second input voltages Vin1 and Vin2 are inputted. The first and second phase delay units 21 and 22 output the first and second output voltages having phases respectively corresponding to the phases of the first and second input voltages Vin1 and Vin2, and the intermediate phase output unit 30 outputs a third output voltage Vout3 having a phase corresponding to an intermediate phase of the first and second input voltages Vin1 and Vin2.
The intermediate phase output unit 30 has a pair of first inverters 31a and 31b whose output ports are mutually connected and to which the first and second input voltages Vin1 and Vin2 are inputted, and a second inverter 32 for inputting the output voltages of the first and second inverters 31a and 31b and outputting a third output voltage Vout3. Further, the first phase delay unit 21 is constituted with a pair of third inverters 21a and 21b connected in series, and the second phase delay unit 22 is constituted with a pair of third inverters 22a and 22b connected in series.
A detailed circuit for each inverter shown in FIG. 1 is shown in FIG. 2. Each inverter includes a PMOS(MP0) transistor and an NMOS(MN0) transistor connected in series. The source of the PMOS(MP0) transistor is applied with a source voltage VDD, the source of the NMOS(MN0) transistor is grounded. Further, the drains of the PMOS(MP0) and NMOS(MN0) transistors are mutually connected. An input voltage Vin is respectively inputted to the gates of the PMOS(MP0) and NMOS(MN0) transistors, and an output voltage Vout is outputted from the drains, that is, from a connection portion of the PMOS(MP0) and NMOS(MN0) transistors. The PMOS(MP0) and NMOS(MN0) transistors operate as switches which are switched according to the input voltage Vin. At this time, a switching mode is the same as follows.
The PMOS(MP0) and NMOS(MN0) transistors are simply described, in the above table, to be turned on or off in operations, but the PMOS(MP0) and NMOS(MN0) transistors vary their resistance values according to a change of a magnitude of the input voltage Vin to operate as variable resistors varying from a short state (or an open state) to the open state (or a short state) substantially. Further, in view of the input voltage, a virtual capacitor C0 is supposed to be connected to an input stage of the inverter.
FIG. 3 is a graph for showing a relationship between the input voltage and output voltages of the inverter shown in FIG. 2. The input voltage Vin, based on the operations as shown in the table, is outputted as an output voltage with its phase inverted. At this time, the switching operations of the PMOS(MP0) and NMOS(MN0) transistors in the inverter are accompanied by a certain time delay, so that, as shown in FIG. 3, the phase-inverted output voltage Vout is outputted after a predetermined delay time.
FIG. 4 is a graph for showing a relationship of the inputs and outputs of a conventional phase blender as shown in FIG. 1.
If the first input voltage Vin1 is inputted to the first phase delay unit 21, the first output voltage Vout1 is outputted in the same waveform as in the first input voltage Vin1 since the first phase delay unit 21 includes the two inverters 21a and 21b. At this time, a waveform delayed by a predetermined delay time by the two inverters 21a and 21b is outputted. With respect to the second input voltage Vin2, the second phase delay unit 22 outputs the second output voltage Vout2 having the same waveform as the second input voltage Vin2 but delayed by the delay time. Accordingly, the first and second phase delay units 21 and 22 output the first and second output voltages Vout1 and Vout2 having phases corresponding to the phases of the first and second input voltages Vin1 and Vin2.
If the first and second input voltages Vin1 and Vin2 are inputted with a certain time difference xcex94t, the intermediate phase output unit 30 outputs the third output voltage Vout3 lagged by xc2xd xcex94t compared to the first output voltage Vout1 and preceded by xc2xd xcex94t compared to the second output voltage Vout2, which is a signal inverted at the intermediate point of the inverting points of the first and second input voltages Vin1 and Vin2. At this time, the third output voltage Vout3 has the same delay time as in the first and second output voltages Vout1 and Vout2. Accordingly, the third output voltage Vout3 is outputted which has a phase corresponding to an intermediate phase of the first and second input voltages Vin1 and Vin2.
When modeling the above phase blender, under the assumption that the two input voltages Vin1 and Vin2 drive the second inverter 32 at different times, a method is used which approximates the above phase blender with mathematical formulas of current sources and RC charges/discharges. Accordingly, as a delay time in one phase blender is obtained, in case that the magnitudes of the first inverters 31a and 32b are the same, the delay time can not be in the center of the edges of the two input voltages Vin1 and Vin2. Accordingly, in order to obtain the output voltage Vout3 of an intermediate phase, the magnitudes of the two inverters 31a and 31b are adjusted. At this time, a ratio of the magnitudes of the inverters 31a and 31b is about 1.2:1.
FIG. 5 is a view for showing a conventional multi-phase generator for generating multiple phases using the phase blender as shown in FIG. 1, which substantially shows a multi-phase generator having eight phase differences.
There is one phase blender 20a present at a first stage of the multi-phase generator, two phase blenders 20b at a second stage, and four phase blenders 20c at a third stage. Of three output voltages from the first stage, the output voltages Vout1 and Vout2 of the phase delay units 21 and 22 are inputted to the phase blenders 20b of the second stage respectively, and the output voltage Vout3 of the intermediate phase output unit 30 is inputted to all the phase blenders 20b of the second stage. The above method is commonly applied to the phase blenders 20a or 20b of the prior stage and the phase blenders 20a or 20b of the next stage. The outputs of the third stage are inputted to a multiplexer 40.
By connecting the phase blenders in multiple steps as stated above, voltages Vout1, Vout2, and Vout3 having a phase difference of xc2xd xcex94t with respect to a phase difference xcex94t of the input voltages Vin1 and Vin2 are outputted at the first stage. By the same principle, voltages having a phase difference of xc2xc xcex94t are outputted at the second stage, and voltages having a phase difference of xe2x85x9 xcex94t are outputted at the third stage. The multiplexer 40 selects one of the eight output voltages having such multiple phases, and, accordingly, one of the eight voltages having a phase difference of xe2x85x9 compared to the phase difference xcex94t of the input voltages Vin1 and Vin2 is selected and outputted.
However, in such a conventional structure, there is a problem in that the size of the entire circuit rapidly increases as the number of signals having intermediate phases to be generated in realizing a multi-phase generator increases. That is, as the number of the stages in the multi-phase generator increases, the number of phase blenders required increases exponentially. Further, the size of the circuit for multiplexing many intermediate signals increases in order to generate signals finally required. Accordingly, there exists a problem in that the size of the circuit, as well as power consumption, exponentially increase.
Further, in modeling the operations of a phase blender corresponding to each cell in a multi-phase generator, there is a problem in that the entire operations rely on the RC filtering. Accordingly, the operation characteristics become nonlinear, so the stabilization of the operations as to changes of processes, voltages, and temperatures becomes particularly important.
The present invention has been devised to solve the above problems, so it is an object of the present invention to provide a multi-phase generator having a smaller circuit size compared to a conventional multi-phase generator of a parallel structure and capable of minimizing a nonlinear effect due to the RC filtering of signals.
Further, it is an object of the present invention to provide a phase blender of a new structure suitable for realizing the above multi-phase generator.
In order to achieve the above objects, the present invention provides a phase blender comprising: first and second phase delay units for respectively inputting first and second input voltages having a certain phase difference from each other, and outputting first and second output voltages having phases corresponding to phases of the first and second input voltages respectively; an intermediate phase output unit having a pair of first inverters the output ports of which are mutually connected and for inputting the first and second input voltages respectively, and a pair of second inverters for inputting the output voltages of the first inverters and outputting third and fourth output voltages respectively; and an output selection unit having a first multiplexer for selectively outputting the first and third output voltages, and a second multiplexer for selectively outputting the second and fourth output voltages.
Here, the first and second inverters each include PMOS and NMOS transistors which perform mutually opposite switching operations according to the magnitudes of the voltages inputted to the gates thereof, and the first and second input voltages are inputted to the gates of the PMOS and NMOS transistors, whereby the third and fourth output voltages have an intermediate phase between the phases of the first and second output voltages.
According to a preferable embodiment of the present invention, the phase blender includes a unit for delaying rising times of the first and second input voltages. Here, the delaying unit may be constituted with a delay inverter having a size smaller than the respective inverters and installed at portions to which the first and second input voltages are inputted. Further, the delaying unit may be a capacitor for charging the first and second input voltages, or a floating inverter having an opened output port and performing a function of a dummy capacitor with respect to the first and second input voltages.
By such delaying unit, the rising times of two input voltages increase, so that a stable intermediate phase can be outputted with respect to the two input voltages having a large phase difference.
In the meantime, a multi-phase generator according to the present invention comprises a first phase blender for inputting first and second input voltages having a certain phase difference and outputting at least two voltages having phases corresponding to phases of the first and second input voltages and voltages having a phase corresponding to an intermediate phase of the input voltages; and at least one second phase blender sequentially connected in series to the first phase blender, and for performing the same function as the first phase blender. The phase blender according to the present invention, as stated above, is employed for each phase blender constituting the multi-phase generator. According to the present invention, a multi-phase generator having a small circuit size and power consumption is provided.